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13
LTC1278
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory interfac-
ing. A separate CONVST is used to initiate a conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.6
s. No external adjustments are required, and
with the typical acquisition time of 250ns, throughput
performance of 500ksps is assured.
Power Shutdown
The LTC1278 provides a shutdown feature that will save
power when the ADC is in inactive periods. To power down
the ADC, Pin 18 (SHDN) needs to be driven low. When in
power shutdown mode, the LTC1278 will not start a
conversion even though the CONVST goes low. All the
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Also, since any potential difference in grounds between
the signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedances as much as
possible.
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at Pin 3 (AGND) or as close as possible to the
ADC. Pin 12 (DGND) and all other analog grounds should
be connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continu-
ously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be elimi-
nated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to iso-
late the ADC data bus.
Figure 11. Internal Logic for Control Inputs CS, RD, CONVST and SHDN
Figure 10. Power Supply Grounding Practice
LTC1278 F10
AIN
AGND
VREF
AVDD
DVDD
DGND
LTC1278
DIGITAL
SYSTEM
0.1
F
+
–
ANALOG GROUND PLANE
GROUND CONNECTION
TO DIGITAL CIRCUITRY
ANALOG
INPUT
CIRCUITRY
3
2
24
17
12
1
0.1
F
10
F
10
F
CONVERSION
START (RISING
EDGE TRIGGER)
LTC1278 F11
BUSY
FLIP
FLOP
CLEAR
Q
D
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
CS
RD
CONVST
SHDN
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